(class uvm_agent) — a component that contains one sequencer, one driver, and one monitor, and which senses and drivers the signals of one SystemVerilog interface.

(class uvm_tlm_analysis_port) — a specific type of transaction-level port that can be connected to zero, one, or many analysis exports and through which a component may call the method write implement [..]

(class uvm_tlm_analysis_export) — a specific type of export that receives an incoming transaction stream from an analysis port.

(class uvm_tlm_analysis_imp) — a specific type of imp that receives an incoming analysis transaction stream. The component class that instantiates an analysis imp must define the method write required [..]

(class uvm_barrier) — an object that causes a set of processes to be blocked until a specified number of processes reach the barrier, at which point all processes waiting at the barrier are allowed to [..]

(class uvm_component) — the structural building block of a UVM verification environment, conceptually equivalent to a Verilog module though implemented as an object in UVM. Components are constructed [..]